CD4006BMS
Logic Diagram and Truth Table
TRUTH TABEL FOR SHIFT REGISTER STAGE
CL
CL
D
0
CL*
D + 1
0
Q
p
TG
n
p
TG
n
D
D + 1
1
1
CL
p
TG
n
CL
p
TG
n
CL
CL
X
NC
Q
Q
TRUTH TABLE FOR OUTPUT FROM TERM 2
CL*
D1 + 4
D1 + 4’
CL
OUT IF
4th OR 5th
STAGE
CL
0
1
0
1
LOGIC DIAGRAM AND TRUTH TABLE (ONE REGISTER STAGE)
X
NC
1 = HIGH
X = DON’T CARE
0 = LOW
*
= LEVEL CHANGE
NC= NO CHANGE
D1 + 4
D1
D
Q
D
Q
D
Q
D
D1 + 4’
LATCH
CL
CL
CL
CL
Q
CL
CL
CL
CL
CL
CL
CLOCK
CL
CL TO 14 MORE STAGES
D
Q
Q
Q
D
Q
Q
D
D2
D3
2 STAGES
D2 + 5
Q
CL
CL
CL
CL
CL
CL
D2 + 4
D3 + 4
D
D
2 STAGES
2 STAGES
CL
Q
CL
CL
CL
D
D4
D
D
Q
Q
D4 + 5
D4 + 4
CL
Q
CL
CL
CL
CL
CL
CL
D1 + 4
LATCH
Q
p
n
D1 + 4
=
CL
CL
CL
CL
p
n
DETAILED LOGIC OF LATCH
CL
Q
LOGIC DIAGRAM WITH DETAIL OF LATCH
7-663
INTERSIL [ Intersil ]
