HS-82C85RH
Waveforms
(Continued)
EFI OR OSC
PCLK
t
SFPC
(NOTE)
SLO/FST
3 EFI PULSES
CLK
t
SFPC
(NOTE)
CLK50
FIGURE 11. SLOW TO FAST CLOCK MODE TRANSITION
NOTE: If t
SFPC
is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK.
X1
15MHz
C
1
X2
C
2
CLK
LOAD
†
PULSE
GENERATOR
EFI
CLK
LOAD
†
CLK50
LOAD
†
V
DD
F/C
CLK50
LOAD
†
F/C
CSYNC
CSYNC
FIGURE 12. CLOCK HIGH AND LOW TIME (USING X1, X2)
FIGURE 13. CLOCK HIGH AND LOW TIME (USING EFI)
VDD
C1
AEN1
X1
CLK
LOAD
†
PULSE
GENERATOR
V
DD
EFI
CLK
LOAD
†
15MHz
F/C
X2
AEN1
READY
RDY2
F/C
AEN2
CSYNC
OSC
LOAD
†
TRIGGER
PULSE
GENERATOR
RDY2
AEN2
CSYNC
READY
LOAD
†
C
2
TRIGGER
PULSE
GENERATOR
FIGURE 14. READY TO CLOCK (USING X1, X2)
FIGURE 15. READY TO CLOCK (USING EFI)
†
C
L
= 50pF
9
FN3044.3
April 20, 2007
INTERSIL [ INTERSIL CORPORATION ]
