5962R9582001VXC 参数 Datasheet PDF下载

HS-82C85RH

Waveforms

(Continued)

t

SHSL

RES

CLK

t

CLIL

RESET

OSC

STARTUP

TIME

OSC

t

OST

t

RST

8192

CYCLES

FIGURE 8. RESET TIMING OSCILLATOR STOPPED (F/C LOW)

NOTE: CLK, CLK50, PCLK remain in the high state until RES goes high and 8192 valid oscillator cycles have been registered by the HS-82C85RH

internal counter t

OST

time period). After RES goes high and CLK, CLK50, PCLK become active, the RESET output will remain high for a minimum

of 16 CLK cycles (t

RST

).

EFI OR OSC

PCLK

SLO/FST

CLK

CLK50

FIGURE 9. SLO/FST TIMING OVERVIEW

195 EFI OR OSC CYCLES

EFI OR OSC

PCLK

t

SFPC

(NOTE)

SLO/FST

t

SFPC

(NOTE)

CLK

CLK50

FIGURE 10. FAST TO SLOW CLOCK MODE TRANSITION

NOTE: If t

SFPC

is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK.

8

FN3044.3

April 20, 2007