HS-26CLV31RH
Pinouts
HS1-26CLV31RH
(16 LD SBDIP)
CDIP2-T16
TOP VIEW
AIN 1
AO 2
AO 3
ENABLE 4
BO 5
BO 6
BIN 7
GND 8
16 VDD
15 DIN
14 DO
13 DO
12 ENABLE
11 CO
10 CO
9 CIN
AIN
AO
AO
ENABLE
BO
BO
BIN
GND
HS9-26CLV31RH
(16 LD FLATPACK)
CDFP4-F16
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
DIN
DO
DO
ENABLE
CO
CO
CIN
Logic Diagram
ENABLE
ENABLE
DIN
CIN
BIN
AIN
DO
DO
CO
CO
BO
BO
AO
AO
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
FN4898.2
May 28, 2009
INTERSIL [ INTERSIL CORPORATION ]
