ISL23428
Block Diagram
V
LOGIC
V
CC
RH0
RH1
SCK
SDI
SDO
CS
SPI
INTERFACE
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
GND
RW0
RL0
RW1
RL1
Pin Configurations
ISL23428
(14 LD TSSOP)
TOP VIEW
GND
V
LOGIC
SDO
SCK
SDI
CS
GND
1
2
3
4
5
6
7
14 V
CC
13
RL0
12
RW0
11 RH0
10
RH1
9
8
RW1
RL1
Pin Descriptions
TSSOP
1, 7
2
3
4
5
6
8
9
10
UTQFN
5, 6, 15
16
1
2
3
4
8
9
10
11
12
13
14
7
SYMBOL
GND
V
LOGIC
SDO
SCK
SDI
CS
RL1
RW1
RH1
RH0
RW0
RL0
V
CC
NC
Ground pin
SPI bus/logic supply
Range 1.2V to 5.5V
Logic Pin - Serial bus data output
(configurable)
Logic Pin - Serial bus clock input
Logic Pin - Serial bus data input
Logic Pin - Active low chip select
DCP1 “low” terminal
DCP1 wiper terminal
DCP1 “high” terminal
DCP0 “high” terminal
DCP0 wiper terminal
DCP0 “low” terminal
Analog power supply.
Range 1.7V to 5.5V
Not Connected
DESCRIPTION
ISL23428
(16 LD UTQFN)
TOP VIEW
V
LOGIC
GND
V
CC
RL0
11
12
13
14
RW0
RH0
RH1
RW1
16
15
14
7
NC
SDO
SCK
SDI
CS
1
2
3
4
5
6
13
12
11
10
9
8
RL1
GND
GND
2
FN7904.0
August 25, 2011
INTERSIL [ INTERSIL CORPORATION ]
