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Intel Advanced+ Boot Block Flash Memory (C3)
Offset
Length
Description
Add.
Hex Code
Value
V
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
0x1E
1
1E:
--C6
12.6 V
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
1
1
1
1
1
1
1
1
“n” such that typical single word program time-out =2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
1F:
20:
21:
22:
23:
24:
25:
26:
--05
--00
--0A
--00
--04
--00
--03
--00
32 µs
NA
1 s
“n” such that typical full chip erase time-out = 2n ms
NA
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
512µs
NA
8s
NA
C.5
Device Geometry Definition
Table 30. Device Geometry Definition
Hex
Code
Offset
0x27
Length
Description
Add.
Value
1
2
“n” such that device size = 2n in number of bytes
27
See Table 31
x8 async
x16 async
x8/x16 async
28:
29:
--01
--00
0x28
Flash device interface:
x16
0
28:00,29:00 28:01,29:00 28:02,29:00
2A:
2B:
--00
--00
0x2A
0x2C
2
“n” such that maximum number of bytes in write buffer = 2n
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions
with one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
1
2C:
--02
2
Erase Block Region 1 Information
2D:
2E:
2F:
30:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
0x2D
0x2D
4
See Table 31
See Table 31
Erase Block Region 2 Information
31:
32:
33:
34:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
14
Datasheet
61
INTEL [ INTEL ]
