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TE28F128J3C-150 参数 Datasheet PDF下载

TE28F128J3C-150图片预览
型号: TE28F128J3C-150
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔StrataFlash闪存( J3 ) [Intel StrataFlash Memory (J3)]
分类和应用: 闪存
文件页数/大小: 72 页 / 909 K
品牌: INTEL [ INTEL ]
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256-Mbit J3 (x8/x16)  
Table 18. Status Register Definitions  
WSMS  
bit 7  
ESS  
bit 6  
ECLBS  
bit 5  
PSLBS  
bit 4  
VPENS  
bit 3  
PSS  
bit2  
DPS  
bit 1  
R
bit 0  
High Z  
When  
Busy?  
Status Register Bits  
Notes  
SR.7 = WRITE STATE MACHINE STATUS  
Check STS or SR.7 to determine block erase,  
program, or lock-bit configuration completion.  
SR[6:0] are not driven while SR.7 = “0.”  
No  
1 = Ready  
0 = Busy  
Yes  
SR.6 = ERASE SUSPEND STATUS  
1 = Block Erase Suspended  
0 = Block Erase in Progress/Completed  
If both SR.5 and SR.4 are “1”s after a block erase or  
lock-bit configuration attempt, an improper  
command sequence was entered.  
SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS  
1 = Error in Block Erasure or Clear Lock-Bits  
0 = Successful Block Erase or Clear Lock-Bits  
Yes  
Yes  
Yes  
SR.4 = PROGRAM AND SET LOCK-BIT STATUS  
1 = Program Error / Error in Setting Lock-Bit  
0 = Successful Program/Set Block Lock Bit  
SR.3 does not provide a continuous programming  
voltage level indication. The WSM interrogates and  
indicates the programming voltage level only after  
Block Erase, Program, Set Block Lock-Bit, or Clear  
Block Lock-Bits command sequences.  
SR.3 = PROGRAMMING VOLTAGE STATUS  
1 = Low Programming Voltage Detected, Operation  
Aborted  
0 = Programming Voltage OK  
Yes  
Yes  
SR.2 = PROGRAM SUSPEND STATUS  
1 = Program suspended  
0 = Program in progress/completed  
SR.1 does not provide a continuous indication of  
block lock-bit values. The WSM interrogates the  
block lock-bits only after Block Erase, Program, or  
Lock-Bit configuration command sequences. It  
informs the system, depending on the attempted  
operation, if the block lock-bit is set. Read the block  
lock configuration codes using the Read Identifier  
Codes command to determine block lock-bit status.  
SR.1 = DEVICE PROTECT STATUS  
1 = Block Lock-Bit Detected, Operation Abort  
0 = Unlock  
SR0 is reserved for future use and should be  
masked when polling the Status Register.  
Yes  
SR0 = RESERVED FOR FUTURE ENHANCEMENTS  
Table 19. Extended Status Register Definitions  
WBS  
bit 7  
Reserved  
Bits 6 -- 0  
High Z  
When  
Busy?  
Status Register Bits  
Notes  
After a Buffer-Write command, XSR.7 = 1 indicates  
that a Write Buffer is available.  
XSR.7 = WRITE BUFFER STATUS  
1 = Write buffer available  
No  
0 = Write buffer not available  
SR[6:0] are reserved for future use and should be  
masked when polling the Status Register.  
Yes  
XSR.6–XSR0 = RESERVED FOR FUTURE  
ENHANCEMENTS  
40  
Datasheet  
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