ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
23h
2Bh
33h
System Memory Map 2 End Address High
System Memory Map 3 End Address High
System Memory Map 4 End Address High
9.4.0.1
Bits 3:0 — End Address 23:20
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7:0 of the System Memory Map 0–4 End Address Low register
(see “System Memory Map 0–4 End Address Low” on page 66).
Bits 7:6 — Card Timer Select
00
01
10
11
Selects Timer Set 0.
Selects Timer Set 1.
Selects Timer Set 1.
Selects Timer Set 1.
This field selects the Timeset registers used to control socket timing for card accesses in this
window address range. Timeset 0 and 1 reset to values compatible with PC Card standards. The
mapping of bits 7:6 to Timeset 0 and 1, as shown in the preceding table, is done for software
compatibility with older ISA bus-based PC Card controllers that use ISA bus wait states instead of
Timeset registers (see “Setup Timing 0–1” on page 84).
9.5
Card Memory Map 0–4 Offset Address Low
Register Name: Card Memory Map 0–4 Offset Address Low
Index: 14h, 1Ch, 24h, 2Ch, 34h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 19:12
RW:00000000
There are five separate Card Memory Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index Card Memory Map Offset Address Low
14h
1Ch
24h
2Ch
34h
Card Memory Map 0 Offset Address Low
Card Memory Map 1 Offset Address Low
Card Memory Map 2 Offset Address Low
Card Memory Map 3 Offset Address Low
Card Memory Map 4 Offset Address Low
Datasheet
67
INTEL [ INTEL ]
