ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
15.4.3 Preventing Dual Interpretation of DMA Handshake Signals...................99
15.4.4 Turning On DMA System .....................................................................100
15.4.5 The DMA Transfer Process..................................................................100
15.4.6 Terminal Count to Card at Conclusion of Transfer..............................100
16.0
Electrical Specifications......................................................................................101
16.1
16.2
16.3
16.4
Absolute Maximum Ratings...............................................................................101
DC Specifications..............................................................................................101
AC Timing Specifications ..................................................................................104
ISA Bus Timing..................................................................................................104
16.4.1 Reset Timing ........................................................................................107
16.4.2 System Interrupt Timing .......................................................................107
16.4.3 General-Purpose Strobe Timing (PD6722 only)...................................108
16.4.4 Input Clock Specification......................................................................108
16.4.5 PC Card Bus Timing Calculations........................................................109
17.0
Package Specifications .......................................................................................121
17.1
17.2
17.3
144-Pin LQFP Package.....................................................................................121
208-Pin MQFP Package....................................................................................122
208-Pin LQFP Package.....................................................................................123
18.0
19.0
Order Numbers Example.....................................................................................124
Appendix A ...............................................................................................................125
19.1
Register Summary Tables.................................................................................125
19.1.1 Operation Registers .............................................................................125
Chip Control Registers ......................................................................................125
I/O Window Mapping Registers.........................................................................127
Memory Window Mapping Registers.................................................................129
Extension Registers ..........................................................................................130
Timing Registers ..............................................................................................133
19.2
19.3
19.4
19.5
19.6
Index
.......................................................................................................................................135
Datasheet
5
INTEL [ INTEL ]
