ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Contents
1.0
2.0
Product Features........................................................................................................9
General Conventions..............................................................................................11
2.1
Numbers and Units..............................................................................................11
3.0
4.0
Pin Information..........................................................................................................12
3.1
3.2
3.3
3.4
Pin Diagrams.......................................................................................................13
Pin Description Conventions ...............................................................................14
Pin Descriptions ..................................................................................................16
Power-On Configuration Summary .....................................................................25
Introduction................................................................................................................27
4.1
System Architecture ............................................................................................27
4.1.1 PC Card Basics......................................................................................27
4.1.2 PD67XX Windowing Capabilities ...........................................................27
4.1.3 PD67XX Functional Blocks ....................................................................30
4.1.4 Interrupts ................................................................................................30
4.1.5 Alternate Functions of Interrupt Pins......................................................31
4.1.6 General-Purpose Strobe Feature...........................................................32
4.1.7 Voltage Sense Pins................................................................................32
4.1.8 PD67XX Power Management ................................................................32
4.1.9 Socket Power Management Features....................................................34
4.1.10 Write FIFO..............................................................................................35
4.1.11 Bus Sizing ..............................................................................................35
4.1.12 Programmable PC Card Timing .............................................................36
4.1.13 DMA Mode Operation for the PD6722 ...................................................36
4.1.14 Selective Data Drive for I/O Windows ....................................................36
Host Access to Registers ....................................................................................36
Power-On Setup..................................................................................................38
4.2
4.3
5.0
6.0
Register Description Conventions....................................................................39
Operation Registers................................................................................................41
6.1
6.2
Index....................................................................................................................41
Data.....................................................................................................................44
7.0
Chip Control Registers ..........................................................................................46
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Chip Revision ......................................................................................................46
Interface Status ...................................................................................................47
Power Control......................................................................................................48
Interrupt and General Control..............................................................................51
Card Status Change............................................................................................52
Management Interrupt Configuration...................................................................54
Mapping Enable ..................................................................................................55
8.0
I/O Window Mapping Registers..........................................................................58
8.1
8.2
I/O Window Control .............................................................................................58
System I/O Map 0–1 Start Address Low .............................................................59
Datasheet
3
INTEL [ INTEL ]
