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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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ISA-to-PC-Card (PCMCIA) Controllers PD6710/22  
Table 1. ISA Bus Interface Pins (Sheet 4 of 4)  
Pin Number  
Pin Name  
Description  
Qty.  
I/O  
Pwr. Drive  
PD6710  
PD6722  
Speaker Out / Chip Select: This I/O pin can  
be used as a digital output to a speaker to  
allow a system to support a PC Cards -  
SPKR pin for fax/modem/voice and audio.  
During reset this pin also serves as a chip-  
configuration input.  
If the level on this pin is low when  
PWRGOOD rises, the PD6710 is configured  
to support cards as a PC Card Socket 2  
device, and the PD6722 is configured to  
support cards as PC Card Socket 2 and  
Socket 3 devices.  
If the level on this pin is high when  
PWRGOOD rises, the PD6710 is configured  
to support cards as a PC Card Socket 0  
device, and the PD6722 is configured to  
support cards as PC Card Socket 0 and  
Socket 1 devices.  
I/O-  
PU  
SPKR_OUT*/  
C_SEL  
142  
202  
1
4
12 mA  
This pin is internally pulled up during reset  
so that default configuration of the chip as a  
Socket 0 (and Socket 1 for PD6722) is  
facilitated. Adhere to the minimum pulse-  
width timing specification for PWRGOOD to  
allow the internal pull-up to operate and  
ensure the default configuration. Refer to  
Bit 6 Socket Indexon page 41 for more  
information on chip configuration.  
After reset operations have completed, this  
pin defaults to high-impedance, and can  
then be enabled as a totem-pole speaker  
output by the setting of a card sockets  
Speaker Enable bit (Misc Control 1  
register, bit 4). This output then becomes  
the negative polarity XOR of each sockets  
BVD2/-SPKR/-LED input that has its  
Speaker Enable bit set. For a description of  
socket index values, refer to Table 11.  
Clock: This input is connected to the ISA  
bus OSC signal. A 14.318-MHz signal is  
used to derive the internal 25-MHz clock  
used for all socket timing. Alternately, a 25-  
MHz clock source can be directly connected  
and the internal synthesizer bypassed.  
CLK  
102  
163  
1
I
4
In default mode this is a status input that can  
be used by software as an indication that the  
V
power supply is stable.  
PP  
-VPP_VALID  
ISA_VCC  
4
3
1
2
I
1
When the PD6722 is in DMA mode (see  
Misc Control 2, bit 6), this input is connected  
to the TC (Terminal Count) signal of the ISA  
bus. In DMA mode, this signal is active-high.  
System Bus V : This supply pin can be  
CC  
set to 3.3 or 5.0 V. The ISA Bus Interface pin  
group (this table) operates at the voltage  
applied to this pin independent of the  
voltage applied to other pin groups.  
76, 135  
138, 195  
PWR  
Datasheet  
19  
 
 
 
 
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