ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 1. ISA Bus Interface Pins (Sheet 2 of 4)
Pin Number
Pin Name
Description
Qty.
I/O
Pwr. Drive
PD6710
PD6722
Memory Read: This input indicates that a
host memory read cycle is occurring.
Connect to ISA signal MEMR*.
MEMR*
MEMW*
83
82
145
1
1
I
I
4
4
–
–
Memory Write: This input indicates that a
host memory write cycle is occurring.
Connect to ISA signal MEMW*.
144
180
Refresh: This input indicates a memory
refresh cycle is occurring and will cause the
PD67XX to ignore memory accesses on the
bus. Connect to ISA signal REFRESH*.
REFRESH*
ALE
119
105
1
1
I
I
4
4
–
–
Address Latch Enable: A high on this input
indicates a valid memory address on the
LA[23:17] bus lines. Connect to ISA signal
BALE.
166
201
Power Good: The PD67XX will be reset
when the POWERGOOD input is low.
Connect to the POWERGOOD signal from
the system power supply; or, if not available,
connect to inverted RESETDRV signal from
ISA bus.
PWRGOOD
141
126
99
1
1
1
I
4
4
4
–
Address Enable: This is an input from the
host CPU bus signal that distinguishes
between DMA and non-DMA bus cycles.
This input should be high for a DMA cycle
and will cause the PD67XX to ignore IOR*
and IOW* except when a PD6722 is
configured for DMA and its DREQ (IRQ10)
and DACK* (IRQ9) signals are active.
Connect to ISA signal AEN.
AEN
187
I
–
When PD67XX is in Suspend mode (see
“Misc Control 2” on page 72), pull this input
high during system power-down for lowest
power consumption.
Memory Select 16: This output is an
acknowledge of 16-bit-wide access support
and is generated by the PD67XX when a
valid 16-bit-word-accessible memory
address has been decoded. Connect to ISA
signal MEMCS16*.
MEMCS16*
160
O-OD
16 mA
I/O Select 16: This output is an
acknowledge for 16-bit-wide access support
and is generated by the PD67XX when a
valid 16-bit word accessible I/O address has
been decoded. Connect to ISA signal
IOCS16*.
IOCS16*
97
158
188
1
1
O-OD
O-TS
4
4
16 mA
16 mA
I/O Channel Ready: This output is driven
low by the PD67XX to lengthen host cycles.
Connect to the ISA bus IOCHRDY signal.
IOCHRDY
127
Datasheet
17
INTEL [ INTEL ]
