8XC52/54/58
SERIAL PORT TIMING - SHIFT REGISTER MODE
e
Test Conditions: Over Operating Conditions; Load Capacitance 80 pF
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
TXLXL
Serial Port
Clock
Cycle Time
1
0.50
284
0.36
167
12 TCLCL
ms
b
10 TCLCL 133
TQVXH Output Data
Setup to Clock
Rising Edge
700
ns
TXHQX Output Data
Hold after Clock
Rising Edge
b
8XC5X
50
0
2 TCLCL 117
ns
ns
b
2 TCLCL 50
8XC5X-24/33
34
10
TXHDX Input Data Hold
After Clock
Rising Edge
0
0
0
ns
b
10 TCLCL 133
TXHDV Clock Rising
Edge to Input
Data Valid
700
283
167
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
272336–15
17
INTEL [ INTEL ]
