£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 32. Primary-Vendor Specific Extended Query (Sheet 2 of 2)
Offset1
P = 0x15
Description
(Optional Flash Features and Commands)
Length
Address
Hex Code
Value
Supported functions after suspend: Read Array,
Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
3E:
--01
0x(P+9)
1
bit 0 Program supported after erase suspend
bit 0 = 1
Yes
3F:
40:
--03
--00
Block status register mask
0x(P+A)
0x(P+B)
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status Register active
bit 1 Block Lock-Down Bit Status active
2
bit 0 = 1
Yes
Yes
bit 1 = 1
V
logic supply highest performance program/
CC
erase voltage
0x(P+C)
1
1
41:
42:
--33
--C0
3.3 V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
V
optimum program/erase supply voltage
PP
0x(P+D)
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
12.0 V
NOTES:
1. The variable P is a pointer which is defined at CFI offset 0x15.
Table 33. Protection Register Information
Offset1
P = 0x35
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Address
Value
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
0x(P+E)
1
43:
--01
01
0x(P+F)
0x(P+10)
(0xP+11)
44:
45:
46:
--80
--00
--03
80h
00h
8 byte
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user programmable. Bits 0–15
point to the Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-
programmable.
4
0x(P+12)
47:
48:
--03
8 byte
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
0x(P+13)
Reserved for future use
NOTES:
1. The variable P is a pointer which is defined at CFI offset 0x15.
Datasheet
63
INTEL [ INTEL ]
