Figures
Tables
Figure 1. Thread Low-power States ...................................................................11
Figure 2. Package Low-power States..................................................................11
Figure 3. Active VCC and ICC Processor Loadline .................................................28
Figure 4. Deeper Sleep VCC and ICC Processor Loadline .......................................29
Table 1. References...........................................................................................9
Table 2. Coordination of Thread Low-power States at the Package Level .................12
Table 3. Voltage Identification Definition ............................................................20
Table 4. BSEL [2:0] Encoding for BCLK Frequency ...............................................23
Table 5. FSB Pin Groups...................................................................................24
Table 6. Processor Absolute Maximum Ratings ....................................................26
Table 7. Voltage and Current Specifications for the Processors...............................27
Table 8. FSB Differential BCLK Specifications ......................................................29
Table 9. AGTL+ Signal Group DC Specifications...................................................30
Table 10. Legacy CMOS Signal Group DC Specifications........................................31
Table 11. Open Drain Signal Group DC Specifications...........................................32
Table 12. Pin-out Arranged by Signal Name........................................................36
Table 13. Signal Description .............................................................................41
Table 14. Power Specifications for the Processor..................................................50
Table 15. Thermal Diode Interface.....................................................................52
Table 16. Thermal Diode Parameters using Transistor Model .................................52
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Datasheet