Low Power Features
2
Low Power Features
2.1
Clock Control and Low-power States
The processor supports low power states at the thread level and the package level. A
thread may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low
power states. Package low power states include Normal, Stop Grant, Stop Grant
Snoop, Sleep and Deep Sleep. When both threads are in a common low-power state
the central power management logic ensures the entire processor enters the
respective package low power state by initiating a P_LVLx (P_LVL2 and P_LVL3) I/O
read to the chipset.
The processor implements two software interfaces for requesting low power states,
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI
P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O
reads are converted to equivalent MWAIT C-state requests inside the processor and do
not directly result in I/O reads on the processor FSB. The monitor address does not
need to be setup before using the P_LVLx I/O read interface. The sub-state hints used
for each P_LVLx read can be configured in a software programmable MSR. If a thread
encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE#
output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic
that individual threads should return to the C0 state and the processor should return
to the Normal state.
Figure 1 shows the thread low-power states. Figure 2 shows the package low-power
states. Table 2 provides a mapping of thread low-power states to package low power
states.
10
Datasheet
INTEL [ INTEL ]
