Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
1.13.4
Boundary Scan Register
Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the
parallel output stage. There are four modes of operation as listed in Table 10.
Table 10. BSR Mode of Operation
Mode
Description
1
2
3
4
Capture
Shift
Update
System Function
Table 11. Supported JTAG Instructions
Name
EXTEST
Code
Description
Mode
Data Register
EXTEST
0000000000000000
1111111111111110
1111111111111110
1111111111001111
1111111111101111
1111111111111111
External Test
BSR
IDCODE
SAMPLE
High Z
ID Code Inspection
Sample Boundary
Force Float
ID REG
BSR
IDCODE
SAMPLE
High Z
Bypass
BSR
Clamp
Clamp
Clamp
BYPASS
Bypass Scan
Bypass
BYPASS
Table 12. Device ID Register
31:28
27:12
11:8
7:1
0
Version
Part ID (hex)
Jedec Continuation Characters
JEDEC ID1
Reserved
0000
2623
0000
111 1110
1
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored.
Intel’s JEDEC ID is FE (1111 1110) which becomes 111 1110.
Datasheet
37
INTEL [ INTEL ]
