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GWIXP425BDT 参数 Datasheet PDF下载

GWIXP425BDT图片预览
型号: GWIXP425BDT
PDF下载: 下载PDF文件 查看货源
内容描述: 网络处理器Intel㈢ IXP42X产品线和IXC1100控制平面处理器 [Intel㈢ IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor]
分类和应用:
文件页数/大小: 134 页 / 1072 K
品牌: INTEL [ INTEL ]
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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor  
5.0  
Electrical Specifications  
5.1  
Absolute Maximum Ratings  
Parameter  
Maximum Rating  
Ambient Air Temperature (Extended)  
Ambient Air Temperature (Commercial)  
Supply Voltage Core  
-40º C to 85º C  
0º C to 70º C  
-0.3 V to 2.1V  
-0.3 V to 3.6V  
-0.3 V to 2.1V  
-0.3 V to 3.6V  
-0.3 V to 2.1V  
-0.3 V to 2.1V  
-0.3 V to 3.6V  
-55o C to 125o C  
Supply Voltage I/O  
Supply Voltage Oscillator (VCCOSC  
)
Supply Voltage Oscillator (VCCOSCP  
)
Supply Voltage PLL (VCCPLL1  
Supply Voltage PLL (VCCPLL2  
Voltage On Any I/O Ball  
Storage Temperature  
)
)
Warning:  
Stressing the device beyond the “absolute maximum ratings” may cause permanent damage. These  
are stress ratings only. Operation beyond the “operating conditions” is not recommended and  
extended exposure beyond the “operating conditions” may affect device reliability.  
5.2  
VCCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements  
To reduce voltage-supply noise on the analog sections of the Intel® IXP42X Product Line of  
Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits (V  
,
CCPLL1  
V
) and oscillator circuit (V  
, V ) require isolated voltage supplies.  
CCPLL2  
CCOSCP CCOSC  
The filter circuits for each supply are shown in the following sections.  
5.2.1  
V
Requirement  
CCPLL1  
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — for a first-  
order filter with a cut-off frequency below 30 MHz — must be connected to the V  
Intel® IXP42X product line and IXC1100 control plane processors.  
pin of the  
CCPLL1  
The ground of both capacitors should be connected to the nearest V supply pin. Both capacitors  
SS  
should be located less than 0.5 inch away from the V  
pin and the associated V pin. In  
CCPLL1  
SS  
order to achieve the 200-nF capacitance, a parallel combination of two 100-nF capacitors may be  
used as long as the capacitors are placed directly beside each other.  
March 2005  
82  
Datasheet  
Document Number: 252479, Revision: 005