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EPM7512AEQC208-7N 参数 Datasheet PDF下载

EPM7512AEQC208-7N图片预览
型号: EPM7512AEQC208-7N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 512-Cell, CMOS, PQFP208,]
分类和应用: 可编程逻辑
文件页数/大小: 64 页 / 961 K
品牌: INTEL [ INTEL ]
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MAX 7000A Programmable Logic Device Data Sheet  
Table 7. MAX 7000A Stand-Alone Verification Times for Different Test Clock Frequencies  
Device  
fTCK  
Units  
10 MHz 5 MHz  
2 MHz  
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz  
EPM7032AE  
EPM7064AE  
EPM7128AE  
EPM7256AE  
EPM7512AE  
EPM7128A (1)  
EPM7256A (1)  
0.00  
0.01  
0.01  
0.02  
0.03  
0.08  
0.13  
0.01  
0.01  
0.02  
0.03  
0.06  
0.14  
0.24  
0.01  
0.02  
0.04  
0.08  
0.15  
0.29  
0.54  
0.02  
0.04  
0.07  
0.15  
0.30  
0.56  
1.06  
0.04  
0.07  
0.14  
0.30  
0.60  
1.09  
2.08  
0.09  
0.18  
0.34  
0.75  
1.49  
2.67  
5.15  
0.18  
0.35  
0.68  
1.49  
2.97  
5.31  
10.27  
0.36  
0.70  
s
s
s
s
s
s
s
1.36  
2.98  
5.94  
10.59  
20.51  
Note to tables:  
(1) EPM7128A and EPM7256A devices can only be programmed with an adaptive algorithm; users programming these  
two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices.  
MAX 7000A devices can be programmed on Windows-based PCs with an  
Altera Logic Programmer card, the MPU, and the appropriate device  
adapter. The MPU performs continuity checks to ensure adequate  
electrical contact between the adapter and the device.  
Programming  
with External  
Hardware  
For more information, see the Altera Programming Hardware Data Sheet.  
f
The Altera software can use text- or waveform-format test vectors created  
with the Altera Text Editor or Waveform Editor to test the programmed  
device. For added design verification, designers can perform functional  
testing to compare the functional device behavior with the results of  
simulation.  
Data I/O, BP Microsystems, and other programming hardware  
manufacturers provide programming support for Altera devices.  
For more information, see Programming Hardware Manufacturers.  
f
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.  
1149.1. Table 8 describes the JTAG instructions supported by MAX 7000A  
devices. The pin-out tables, available from the Altera web site  
(http://www.altera.com), show the location of the JTAG control pins for  
IEEE Std.  
1149.1 (JTAG)  
Boundary-Scan  
each device. If the JTAG interface is not required, the JTAG pins are  
Support  
available as user I/O pins.  
20  
Altera Corporation  
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