MAX 7000A Programmable Logic Device Data Sheet
Table 27. EPM7256A Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min Max Min Max Min Max Min Max
tIN
tIO
Input pad and buffer delay
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
ns
ns
I/O input pad and buffer
delay
tFIN
Fast input delay
2.4
2.8
0.5
2.5
2.5
0.2
3.0
3.5
0.6
3.1
3.1
0.3
3.4
4.7
0.8
4.2
4.2
0.4
3.8
5.6
1.0
5.0
5.0
0.5
ns
ns
ns
ns
ns
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable
delay
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
0.3
0.8
5.3
4.0
4.5
9.0
4.0
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.5
1.0
5.5
5.0
5.5
10.0
5.0
0.6
1.1
5.6
5.0
5.5
ns
ns
ns
ns
ns
Output buffer and pad
delay, slow slew rate = off (5)
VCCIO = 2.5 V
Output buffer and pad
delay slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
Output buffer enable
delay slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
Output buffer enable
delay slow slew rate = off (5)
VCCIO = 2.5 V
Output buffer enable
C1 = 35 pF
10.0 ns
delay slow slew rate = on
VCCIO = 2.5 V or 3.3 V
Output buffer disable
delay
C1 = 5 pF
5.0
ns
tSU
tH
Register setup time
Register hold time
1.0
1.7
1.2
1.3
2.4
1.4
1.7
3.7
1.4
2.0
4.7
1.4
ns
ns
ns
tFSU
Register setup time of fast
input
tFH
Register hold time of fast
input
1.3
1.6
1.6
1.6
ns
Altera Corporation
49
INTEL [ INTEL ]
