MAX 7000A Programmable Logic Device Data Sheet
Table 26. EPM7256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-12
tPD1
tPD2
Input to non-registered
output
C1 = 35 pF
6.0
7.5
10.0
12.0 ns
(2)
I/O input to non-
registered output
C1 = 35 pF
6.0
7.5
10.0
12.0 ns
(2)
tSU
tH
Global clock setup time (2)
3.7
0.0
2.5
4.6
0.0
3.0
6.2
0.0
3.0
7.4
0.0
3.0
ns
ns
ns
Global clock hold time
(2)
tFSU
Global clock setup time
of fast input
tFH
Global clock hold time of
fast input
0.0
0.0
1.0
0.0
1.0
0.0
1.0
ns
tCO1
Global clock to output
delay
C1 = 35 pF 1.0
3.3
6.2
4.2
7.8
5.5
6.6
ns
tCH
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
3.0
3.0
3.0
3.0
1.0
2.7
1.0
4.0
4.0
1.4
4.0
4.0
4.0
1.6
5.1
ns
ns
ns
ns
tCL
tASU
tAH
(2)
(2)
0.8
1.9
tACO1
Array clock to output
delay
C1 = 35 pF 1.0
1.0 10.3
1.0 12.4 ns
(2)
tACH
tACL
Array clock high time
Array clock low time
3.0
3.0
3.0
3.0
3.0
4.0
4.0
4.0
4.0
4.0
4.0
ns
ns
ns
tCPPW
Minimum pulse width for (3)
3.0
clear and preset
tCNT
Minimum global clock
period
(2)
6.4
6.4
8.0
8.0
10.7
93.5
12.8 ns
MHz
fCNT
Maximum internal global (2), (4)
156.3
156.3
125.0
125.0
78.1
78.1
clock frequency
tACNT
fACNT
Minimum array clock
period
(2)
10.7
12.8 ns
MHz
Maximum internal array (2), (4)
93.5
clock frequency
48
Altera Corporation
INTEL [ INTEL ]
