MAX 7000A Programmable Logic Device Data Sheet
Table 15. EPM7032AE Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7
Unit
-4
-10
Min
Max Min
Max
Min Max
tIN
tIO
Input pad and buffer delay
0.7
0.7
1.2
1.2
1.5
1.5
ns
ns
I/O input pad and buffer
delay
tFIN
Fast input delay
2.3
1.9
0.5
1.5
0.6
0.0
0.8
2.8
3.1
0.8
2.5
1.0
0.0
1.3
3.4
4.0
1.0
3.3
1.2
0.0
1.8
ns
ns
ns
ns
ns
ns
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
tOD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
tOD2
tOD3
tZX1
tZX2
tZX3
Output buffer and pad
1.3
5.8
4.0
4.5
9.0
4.0
1.8
6.3
4.0
4.5
9.0
4.0
2.3
6.8
ns
ns
ns
ns
ns
delay, slow slew rate = off (5)
VCCIO = 2.5 V
Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
Output buffer enable delay, C1 = 35 pF
slow slew rate = off
5.0
VCCIO = 3.3 V
Output buffer enable delay, C1 = 35 pF
5.5
slow slew rate = off
VCCIO = 2.5 V
(5)
Output buffer enable delay, C1 = 35 pF
slow slew rate = on
10.0
VCCIO = 3.3 V
tXZ
tSU
tH
Output buffer disable delay C1 = 5 pF
Register setup time
5.0
ns
ns
ns
ns
1.3
0.6
1.0
2.0
1.0
1.5
2.8
1.3
1.5
Register hold time
tFSU
Register setup time of fast
input
tFH
Register hold time of fast
input
1.5
1.5
1.5
ns
tRD
Register delay
0.7
0.6
1.2
1.0
1.5
1.3
ns
ns
tCOMB
Combinatorial delay
Altera Corporation
31
INTEL [ INTEL ]
