欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM3064ATC44-4NAG 参数 Datasheet PDF下载

EPM3064ATC44-4NAG图片预览
型号: EPM3064ATC44-4NAG
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 4.5ns, CMOS, PQFP44, TQFP-44]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 709 K
品牌: INTEL [ INTEL CORPORATION ]
 浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第1页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第2页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第4页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第5页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第6页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第7页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第8页浏览型号EPM3064ATC44-4NAG的Datasheet PDF文件第9页  
MAX 3000A Programmable Logic Device Family Data Sheet
Table 2. MAX 3000A Speed Grades
Device
–4
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Speed Grade
–5
–6
–7
v
v
v
v
v
v
–10
v
v
v
v
v
v
v
The MAX 3000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high–density small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A architecture easily integrates multiple devices
ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including
PLCC, PQFP, and TQFP packages. See
Table 3. MAX 3000A Maximum User I/O Pins
Device
44–Pin
PLCC
34
34
44–Pin
TQFP
34
34
100–Pin 144–Pin 208–Pin 256-Pin
TQFP
TQFP
PQFP FineLine
BGA
66
80
96
116
158
172
98
161
208
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Note:
(1)
When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or
boundary–scan testing, four I/O pins become JTAG pins.
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The user–configurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debugging cycles, and can be
programmed and erased up to 100 times.
Altera Corporation
3