5–22
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–27. External Timing Input Delay Adders (Part 2 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
I/O Standard
Min Max Min Max Min Max Min Max Min Max Min Max Unit
3.3-V LVCMOS Without Schmitt
Trigger
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
535
37
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
ps
ps
ps
ps
ps
ps
ps
With Schmitt
Trigger
334
23
434
30
387
42
434
43
442
43
2.5-V LVTTL /
LVCMOS
Without Schmitt
Trigger
With Schmitt
Trigger
339
291
681
0
441
378
885
0
543
466
1,090
0
429
378
681
0
476
373
622
0
483
373
658
0
1.8-V LVTTL /
LVCMOS
Without Schmitt
Trigger
1.5-V LVCMOS Without Schmitt
Trigger
3.3-V PCI
Without Schmitt
Trigger
Table 5–28. External Timing Input Delay tGLOB Adders for GCLK Pins
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
I/O Standard
3.3-V LVTTL Without Schmitt
Min Max Min Max Min Max Min Max Min Max Min Max Unit
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
400
0
—
—
—
—
—
—
—
—
—
0
493
0
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
Trigger
With Schmitt
Trigger
308
0
387
0
434
0
442
0
3.3-V LVCMOS Without Schmitt
Trigger
With Schmitt
Trigger
308
21
400
27
493
33
387
42
434
43
442
43
2.5-V LVTTL /
LVCMOS
Without Schmitt
Trigger
With Schmitt
Trigger
423
353
855
6
550
459
1,111
7
677
565
1,368
9
429
378
681
0
476
373
622
0
483
373
658
0
1.8-V LVTTL /
LVCMOS
Without Schmitt
Trigger
1.5-V LVCMOS Without Schmitt
Trigger
3.3-V PCI
Without Schmitt
Trigger
MAX II Device Handbook
© August 2009 Altera Corporation
INTEL [ INTEL ]
