5–26
Chapter 5: DC and Switching Characteristics
Referenced Documents
Table 5–34.
MAX II JTAG Timing Parameters (Part 2 of 2)
Symbol
t
JP SU
t
JP H
t
JP CO
t
JP ZX
t
JP XZ
t
JS SU
t
JS H
t
JS CO
t
JS ZX
t
JS XZ
Notes to
(1) Minimum clock period specified for 10 pF load on the
TDO
pin. Larger loads on
TDO
will degrade the maximum
TCK
frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V
LVTTL/LVCMOS and 1.5-V LVCMOS, the t
JPS U
minimum is 6 ns and t
J PC O
, t
JP ZX
, and t
JP XZ
are maximum values at 35 ns.
Parameter
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min
8
10
—
—
—
8
10
—
—
—
Max
—
—
15
15
15
—
—
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Referenced Documents
This chapter references the following documents:
■
I/O Structure
section in the
chapter in the
MAX II Device
Handbook
chapter in the
MAX II Device
Handbook
chapter in volume 3 of the
Quartus II Handbook
chapter in the
MAX II Device
Handbook
chapter in the
MAX II Device Handbook
chapter in the
MAX II Device
Handbook
■
■
■
■
■
■
INTEL [ INTEL CORPORATION ]
