欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM570F256C5N 参数 Datasheet PDF下载

EPM570F256C5N图片预览
型号: EPM570F256C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.7ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
 浏览型号EPM570F256C5N的Datasheet PDF文件第10页浏览型号EPM570F256C5N的Datasheet PDF文件第11页浏览型号EPM570F256C5N的Datasheet PDF文件第12页浏览型号EPM570F256C5N的Datasheet PDF文件第13页浏览型号EPM570F256C5N的Datasheet PDF文件第15页浏览型号EPM570F256C5N的Datasheet PDF文件第16页浏览型号EPM570F256C5N的Datasheet PDF文件第17页浏览型号EPM570F256C5N的Datasheet PDF文件第18页  
2–6  
Chapter 2: MAX II Architecture  
Logic Elements  
Figure 2–5. LAB-Wide Control Signals  
Dedicated  
4
LAB Column  
Clocks  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
labclkena2  
labclkena1  
syncload  
labclr2  
addnsub  
Local  
Interconnect  
labclk1  
labclk2  
asyncload  
or labpre  
labclr1  
synclr  
Logic Elements  
The smallest unit of logic in the MAX II architecture, the LE, is compact and provides  
advanced features with efficient logic utilization. Each LE contains a four-input LUT,  
which is a function generator that can implement any function of four variables. In  
addition, each LE contains a programmable register and carry chain with carry-select  
capability. A single LE also supports dynamic single-bit addition or subtraction mode  
selectable by an LAB-wide control signal. Each LE drives all types of interconnects:  
local, row, column, LUT chain, register chain, and DirectLink interconnects. See  
Figure 2–6.  
MAX II Device Handbook  
© October 2008 Altera Corporation