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EPM570F256C5N 参数 Datasheet PDF下载

EPM570F256C5N图片预览
型号: EPM570F256C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.7ns, 440-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 982 K
品牌: INTEL [ INTEL ]
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Chapter 2: MAX II Architecture  
2–3  
Functional Description  
Table 2–1. MAX II Device Resources  
LAB Rows  
Short LAB Rows  
Devices  
EPM240  
UFM Blocks  
LAB Columns  
Long LAB Rows  
(Width) (1)  
Total LABs  
1
1
1
1
6
4
4
24  
57  
EPM570  
12  
16  
20  
3 (3)  
EPM1270  
7
3 (5)  
127  
221  
EPM2210  
10  
3 (7)  
Note to Table 2–1:  
(1) The width is the number of LAB columns in length.  
Figure 2–2 shows a floorplan of a MAX II device.  
Figure 2–2. MAX II Device Floorplan (Note 1)  
I/O Blocks  
I/O Blocks  
Logic Array  
Blocks  
Logic Array  
Blocks  
2 GCLK  
Inputs  
2 GCLK  
Inputs  
I/O Blocks  
UFM Block  
CFM Block  
Note to Figure 2–2:  
(1) The device shown is an EPM570 device. EPM1270 and EPM2210 devices have a similar floorplan with more LABs. For EPM240 devices, the CFM  
and UFM blocks are located on the left side of the device.  
© October 2008 Altera Corporation  
MAX II Device Handbook