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EPM1270GF100I4N 参数 Datasheet PDF下载

EPM1270GF100I4N图片预览
型号: EPM1270GF100I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL ]
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MAX II Architecture  
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local  
interconnect, a look-up table (LUT) chain, and register chain connection  
lines. There are 26 possible unique inputs into an LAB, with an additional  
10 local feedback input lines fed by LE outputs in the same LAB. The local  
interconnect transfers signals between LEs in the same LAB. LUT chain  
connections transfer the output of one LE’s LUT to the adjacent LE for fast  
sequential LUT connections within the same LAB. Register chain  
connections transfer the output of one LE’s register to the adjacent LE’s  
register within an LAB. The Quartus® II software places associated logic  
within an LAB or adjacent LABs, allowing the use of local, LUT chain,  
and register chain connections for performance and area efficiency.  
Figure 2–3 shows the MAX II LAB.  
Logic Array  
Blocks  
Figure 2–3. MAX II LAB Structure  
Row Interconnect  
Column Interconnect  
LE0  
LE1  
LE2  
LE3  
Fast I/O connection  
to IOE (1)  
Fast I/O Connection  
to IOE (1)  
DirectLink  
DirectLink  
interconnect from  
adjacent LAB  
or IOE  
interconnect from  
adjacent LAB  
or IOE  
LE4  
LE5  
LE6  
LE7  
DirectLink  
DirectLink  
interconnect to  
adjacent LAB  
or IOE  
interconnect to  
adjacent LAB  
or IOE  
LE8  
LE9  
Logic Element  
LAB  
Local Interconnect  
Note to Figure 2–3:  
(1) Only from LABs adjacent to IOEs.  
Altera Corporation  
August 2006  
Core Version a.b.c variable  
2–5  
MAX II Device Handbook, Volume 1