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Package
Package
Figure 6 and Figure 7 show the configuration device package pin-outs.
Figure 6. EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441 Package Pin-Out Diagrams (1)
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
N.C.
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
N.C.
DCLK
N.C.
N.C.
N.C.
N.C.
OE
3
2
1
20 19
18
DCLK
N.C.
4
5
6
7
8
VCC
N.C.
17
16
15
14
DATA
DCLK
OE
1
2
3
4
8
7
6
5
VCC
N.C.
N.C.
VCC
nCASC(2)
GND
N.C.
OE
N.C.
N.C.
nCS
N.C.
9
10 11 12 13 14 15 16
9
10 11 12 13
32-Pin TQFP
20-Pin PLCC
8-Pin PDIP
EPC1441
EPC1064
EPC1064V
EPC1
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
EPC1441
EPC1213
EPC1064
EPC1064V
Notes to Figure 6:
(1) EPC1 and EPC1441 devices are one-time programmable devices. ISP is not available in these devices.
(2) The nCASCpin is available on EPC1 devices, which allows them to be cascaded. For EPC1441 devices, nCASCis a reserved pin and should
be left unconnected.
Figure 7. EPC2 Package Pin-Out Diagrams
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
N.C.
DCLK
VCCSEL
N.C.
24
23
22
21
20
19
18
N.C.
VPP
N.C.
N.C.
3
2
1
20 19
18
DCLK
VCCSEL
N.C.
4
5
6
7
8
VPP
N.C.
N.C.
17
16
15
14
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
OE
N.C.
VPPSEL
VPPSEL
8
17
16
N.C.
OE
9
10 11 12 13 14 15
9
10 11 12 13
32-Pin TQFP
20-Pin PLCC
f For more information about package outlines and drawings, refer to the Package and
Thermal Resistance page.
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
INTEL [ INTEL ]
