Pin Information
Page 21
Pin Information
Table 20 lists the pin functions of the EPC1, EPC2, and EPC1441 devices during device
configuration.
f For more information about pin information of EPC devices, refer to the Enhanced
Configuration (EPC) Devices Datasheet.
f For more information about pin information of EPCS devices, refer to the Serial
Configuration (EPCS) Devices Datasheet.
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 1 of 3)
Pin Number
Pin Name
Pin Type
Description
8-Pin
20-Pin
PLCC
32-Pin
(1)
(2)
PDIP
TQFP
Serial data output. The DATApin connects to the DATA0pin
of the FPGA. DATAis latched into the FPGA on the rising
edge of DCLK
.
DATA
1
2
31
Output
The DATApin is tri-stated before configuration and when
the nCSpin is high. After configuration, the EPC2 device
drives DATAhigh, while the EPC1 and EPC1441 device
tri-state DATA
.
Clock output when configuring with a single configuration
device or when the configuration device is the first
(master) device in a chain. Clock input for the next (slave)
configuration devices in a chain. The DCLKpin connects to
the DCLKpin of the FPGA.
Rising edges on DCLKincrement the internal address
counter and present the next bit of data on the DATApin.
The counter is incremented only if the OEinput is held
high, the nCSinput is held low, and all configuration data
has not been transferred to the target device.
DCLK
2
4
2
Bidirectional
After configuration or when OE is low, the EPC1, EPC2 and
EPC1441 device drive DCLKlow.
Output enable (active high) and reset (active low). The OE
pin connects to the nSTATUSpin of the FPGA.
A low logic level resets the address counter. A high logic
level enables DATAand the address counter to count. If this
pin is low (reset) during configuration, the internal
Open-drain
oscillator becomes inactive and DCLKdrives low. For more
OE
3
8
7
bidirectional information, refer to “Error Detection Circuitry” on page 9.
The OE pin has an internal programmable 1-k resistor in
EPC2 devices. If internal pull-up resistors are used, do not
use external pull-up resistors on these pins. You can
disable the internal pull-up resistors through the Disable
nCS and OE pull-ups on configuration device option.
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices
INTEL [ INTEL ]
