Power and Operation
Page 11
Table 3 lists the relationship between the VCC and VPP voltage levels and the required
logic level for VCCSELand VPPSELpins. A high logic level means the pin should be
connected to VCC, while a low logic level means the pin should be connected to GND.
Table 3. VCCSEL and VPPSEL Pin Functions on the EPC2 Device
VCC Voltage Level
(V)
VPP Voltage Level
(V)
VCCSEL Pin Logic
Level
VPPSEL Pin Logic
Level
3.3
3.3
5.0
3.3
5.0
5.0
High
High
Low
High
Low
Low
At a 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except for DATA, DCLK, and
nCASCpins. The DATAand DCLKpins are used only to interface between the EPC2
device and the FPGA it is configuring. Table 4 lists the voltage tolerences of all EPC2
device pins.
Table 4. EPC2 Device Input and Bidirectional Pin Voltage Tolerance
5.0-V Operation
3.3-V Operation
Pin
5.0-V Tolerant
3.3-V Tolerant
5.0-V Tolerant
3.3-V Tolerant
DATA
DCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
n
CASC
OE
CS
n
VCCSEL
VPPSEL
nINIT_CONF
TDI
TMS
TCK
If one EPC1, EPC2, or EPC1441 configuration device is powered at 3.3 V, the nSTATUS
and CONF DONEpull-up resistors must be connected to 3.3 V. If these configuration
devices are powered at 5.0 V, the nSTATUSand CONF
connected to either 3.3 V or 5.0 V.
_
_
DONEpull-up resistors can be
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices
INTEL [ INTEL ]
