Chapter 1: Cyclone III Device Datasheet
1–25
Switching Characteristics
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 2 of 2)
Parameter
Duty cycle jitter
Symbol
Min
Max
Unit
tJIT(duty)
-150
150
ps
Notes to Table 1–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specifications
Table 1–35 lists the worst case duty cycle distortion for Cyclone III devices.
(1), (2)
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins
C6
C7, I7
Max
55
C8, A7
Symbol
Unit
Min
Max
Min
Min
45
Max
Output Duty Cycle
45
55
45
55
%
Notes to Table 1–35:
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
and general purpose I/O pins.
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
I/O standard and current strength.
OCT Calibration Timing Specification
Table 1–36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III devices.
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
(1)
Power-Up
Symbol
Description
Maximum
Unit
Duration of series OCT with
calibration at device power-up
tOCTCAL
20
µs
Notes to Table 1–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
Table 1–37 and Table 1–38 list IOE programmable delay for Cyclone III devices.
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 1 of 2)
Max Offset
Number
Paths
Affected
Min
Offset
Parameter
of
Fast Corner
A7, I7 C6
Slow Corner
C8
Unit
Settings
C6
C7
I7
A7
Pad to I/O
dataout to
core
Input delay from pin to
internal cells
7
8
0
0
1.211 1.314 2.175
2.32
2.386 2.366
2.49
ns
ns
Input delay from pin to Pad to I/O
1.203 1.307
2.19
2.387
2.54
2.43
2.545
input register
input register
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
INTEL [ INTEL ]
