DC & Switching Characteristics
Table 5–103. Document Revision History (Part 3 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
January 2005,
v2.0
●
●
Updated the “Power Consumption” section.
Added the “High-Speed I/O Specifications” and
“On-Chip Termination Specifications” sections.
Removed the ESD Protection Specifications
section.
Updated Tables 5–3 through 5–13, 5–16 through
5–18, 5–21, 5–35, 5–39, and 5–40.
Updated tables in “Timing Model” section.
Added Tables 5–30 and 5–31.
—
●
●
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●
October 2004,
v1.2
●
●
Updated Table 5–3.
Updated introduction text in the “PLL Timing
Specifications” section.
—
—
July 2004, v1.1
●
●
●
Re-organized chapter.
Added typical values and COUTFB to Table 5–32.
Added undershoot specification to Note (4) for
Tables 5–1 through 5–9.
●
●
●
Added Note (1) to Tables 5–5 and 5–6.
Added VID and VICM to Table 5–10.
Added “I/O Timing Measurement Methodology”
section.
●
●
Added Table 5–72.
Updated Tables 5–1 through 5–2 and Tables 5–24
through 5–29.
February 2004, Added document to the Stratix II Device Handbook.
v1.0
—
Altera Corporation
April 2011
5–99
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
