JTAG Timing Specifications
Table 5–100. DQS Phase Offset Delay Per Stage
Notes (1), (2), (3)
Max Unit
Speed Grade
Min
-3
-4
-5
9
9
9
14
14
15
ps
ps
ps
Notes to Table 5–100:
(1) The delay settings are linear.
(2) The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
(3) The typical value equals the average of the minimum and maximum values.
Table 5–101. DDIO Outputs Half-Period Jitter
Name Description
Notes (1), (2)
Max
Unit
tOUTHALFJITTER Half-period jitter (PLL driving DDIO outputs) 200
ps
Notes to Table 5–101:
(1) The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
(2) The half-period jitter was characterized using a PLL driving DDIO outputs.
Figure 5–10 shows the timing requirements for the JTAG signals.
JTAG Timing
Specifications
Figure 5–10. Stratix II JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
5–96
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
INTEL [ INTEL ]
