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EP2S60F484I4N 参数 Datasheet PDF下载

EP2S60F484I4N图片预览
型号: EP2S60F484I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 3022 CLBs, 717MHz, 60440-Cell, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 248 页 / 2983 K
品牌: INTEL [ INTEL ]
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DC & Switching Characteristics  
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 2  
of 2)  
I/O Standard  
CapacitiveLoad Unit  
SSTL-2 Class II  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
SSTL-18 Class I  
SSTL-18 Class II  
1.5-V HSTL Class I  
1.5-V HSTL Class II  
1.8-V HSTL Class I  
1.8-V HSTL Class II  
1.2-V HSTL with OCT  
Differential SSTL-2 Class I  
Differential SSTL-2 Class II  
Differential SSTL-18 Class I  
Differential SSTL-18 Class II  
1.5-V Differential HSTL Class I  
1.5-V Differential HSTL Class II  
1.8-V Differential HSTL Class I  
1.8-V Differential HSTL Class II  
LVDS  
HyperTransport  
LVPECL  
Altera Corporation  
April 2011  
5–53  
Stratix II Device Handbook, Volume 1  
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