Adaptive Logic Modules
signal with asynchronous load data input tied high. When the
asynchronous load/preset signal is used, the labclkena0signal is no
longer available.
The LAB row clocks [5..0]and LAB local interconnect generate the
TM
LAB-wide control signals. The MultiTrack interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclr1
labclk0
syncload
labclk1
labclk2
labclkena2
labclkena0
or asyncload
or labpreset
labclkena1
labclr0
synclr
The basic building block of logic in the Stratix II architecture, the adaptive
logic module (ALM), provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based
resources that can be divided between two adaptive LUTs (ALUTs). With
up to eight inputs to the two ALUTs, one ALM can implement various
combinations of two functions. This adaptability allows the ALM to be
Adaptive Logic
Modules
2–6
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
INTEL [ INTEL ]
