R
Tables
Table 2-1. Host Interface Reset and S3 States ................................................................46
Table 2-2. System Memory (DDR2) Reset and S3 States ...............................................47
Table 2-3. System Memory (DDR) Reset and S3 States .................................................49
Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States ...................................50
Table 2-5. DMI Reset and S3 States ................................................................................50
Table 2-6. Clocking Reset and S3 States.........................................................................51
Table 2-7. MISC Reset and S3 States..............................................................................51
Table 2-8. DAC Reset and S3 States (Intel® 82915G/82915GV/82915GL/82910GL
GMCH only) ...............................................................................................................51
Table 3-1. Device Number Assignment for Internal (G)MCH Devices .............................57
Table 4-1. Device 0 Function 0 Register Address Map Summary....................................65
Table 6-1. Egress Port Register Address Map ...............................................................109
Table 7-1. DMI Register Address Map Summary...........................................................115
Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0) ...........125
Table 9-1. Integrated Graphics Device Register Address Map (D2:F0).........................173
Table 10-1. Device 2 Function 1 Register Address Map Summary ...............................193
Table 11-1. Expansion Area Memory Segments............................................................209
Table 11-2. Extended System BIOS Area Memory Segments.......................................210
Table 11-3. System BIOS Area Memory Segments .......................................................210
Table 11-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB
TSEG .......................................................................................................................212
Table 11-5. SMM Space Table .......................................................................................218
Table 11-6. SMM Control Table......................................................................................218
Table 12-1. Sample System Memory Organization with Interleaved Channels .............225
Table 12-2. Sample System Memory Organization with Asymmetric Channels ............225
Table 12-3. DDR / DDR2 DIMM Supported Configurations ...........................................228
Table 12-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) ......229
Table 12-5. DRAM Address Translation (Dual Channel Symmetric Mode) ...................230
Table 12-6. Display Port Characteristics ........................................................................248
Table 12-7. Analog Port Characteristics.........................................................................249
Table 13-1. Absolute Maximum Ratings.........................................................................255
Table 13-2. Non-Memory Power Characteristics............................................................257
Table 13-3. DDR Power Characteristics.........................................................................258
Table 13-4. DDR2 Power Characteristics.......................................................................258
Table 13-5. Signal Groups..............................................................................................259
Table 13-6. DC Characteristics3 .....................................................................................262
Table 13-7. RGB/CRT DAC Display DC Characteristics (Functional Operating Range:
VCCA_DAC = 2.5 V ±5%) .......................................................................................265
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)..............271
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name).............300
Table 14-3. GMCH/MCH Ballout for DDR Systems (Sorted by Ball Number)................333
Table 14-4. GMCH/MCH Ballout for DDR Systems (Sorted by Signal Name)...............365
Table 15-1. Complimentary Pins to Drive.......................................................................399
Table 15-2. XOR Chain Outputs for both DDR and DDR2.............................................401
Table 15-3. DDR XOR Chain #0.....................................................................................402
Table 15-4. DDR XOR Chain #1.....................................................................................404
Table 15-5. DDR XOR Chain #2.....................................................................................406
Table 15-6. DDR XOR Chain #3.....................................................................................407
Table 15-7. DDR XOR Chain #4.....................................................................................408
Table 15-8. DDR XOR Chain #5.....................................................................................409
Table 15-9. DDR XOR Chain #6.....................................................................................410
12
Datasheet
INTEL [ INTEL ]
