Networking Silicon — 82551IT
Table 57. Measure and Test Condition Parameters
Vtest
0.4VCC
V
V
V
V
V
V
Min Delay
Vstep (rising edge)
0.285VCC
Max Delay
Min Delay
Max Delay
Vstep (falling edge)
Vmax
0.615VCC
0.4VCC
1
Input Signal Edge
Rate
V/ns
NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed
for testing input timing.
11.4.2.2
PCI Timings
Table 58. PCI Timing Parameters
Symbol
Parameter
Min
Max
Units
Notes
T14 tval
PCI CLK to Signal Valid Delay
2
11
ns
1, 2, 3
PCI CLK to Signal Valid Delay (point-
to-point)
T15 tval(ptp)
2
2
12
ns
1, 2, 3
T16 ton
T17 toff
T18 tsu
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
ns
ns
ns
1
1
28
7
3, 4
PCI Input Setup Time to CLK (point-to-
point)
T19 tsu(ptp)
10
ns
3, 4
T20 th
Input Hold Time from CLK
0
1
ns
5
5
T21 trst
Reset Active Time After Power Stable
ms
PCI Reset Active Time After CLK
Stable
T22 Trst-clk
T23 Trst-off
100
clocks
ns
5
Reset Active to Output Float Delay
40
5, 6
NOTES:
1. Timing measurement conditions are illustrated in Figure 21.
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
4.2.3.2.
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
and input setup times than bussed signals. All other signals are bussed.
4. Timing measurement conditions are illustrated in Figure 22.
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI interface output drivers are floated when RST# is active.
11.4.2.3
Flash Interface Timings
The 82551IT is designed to support up to 150 ns of Flash access time. The V signal in the Flash
PP
implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled
only by the FLWE# pin.
Table 59 provides the timing parameters for the Flash interface signals. The timing parameters are
illustrated in Figure 23 and Figure 24.
Datasheet
83
INTEL [ INTEL ]
