82551IT — Networking Silicon
11.4.2
Timing Parameters
11.4.2.1
Measurement and Test Conditions
Figure 21, Figure 22, and Table 57 define the conditions under which timing measurements are
done. The component test guarantees that all timings are met with minimum clock slew rate
(slowest edge) and voltage swing. The design must guarantee that minimum timings are also met
with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must
guarantee proper input operation for input voltage swings and slew rates that exceed the specified
test conditions.
Figure 21. Output Timing Measurement Conditions
V_th
V_tl
V_test
CLK
T_val
OUTPUT
DELAY
V_step
Tri-State
OUTPUT
V_test
T_on
V_test
T_off
Figure 22. Input Timing Measurement Conditions
V_th
V_tl
V_test
T_h
CLK
T_su
V_th
V_tl
inputs
valid
V_test
V_test
V_max
INPUT
Table 57. Measure and Test Condition Parameters
Symbol
PCI Level
Units
Notes
Vth
Vtl
0.6VCC
0.2VCC
V
V
82
Datasheet
INTEL [ INTEL ]
