Networking Silicon — 82551IT
Contents
1.0
2.0
3.0
4.0
Introduction.........................................................................................................................1
1.1
1.2
1.3
1.4
Overview ...............................................................................................................1
Byte Ordering ........................................................................................................1
References............................................................................................................1
Product Ordering Codes........................................................................................2
Architectural Overview .......................................................................................................3
2.1
2.2
2.3
2.4
Parallel Subsystem Overview................................................................................3
FIFO Subsystem Overview ...................................................................................3
10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4
10/100 Mbps Physical Layer Unit..........................................................................4
Performance Enhancements..............................................................................................5
3.1
3.2
3.3
3.4
Multiple Priority Transmit Queues .........................................................................5
Early Release........................................................................................................5
Hardware Integrity Support ...................................................................................6
Management Data Interface MDI/MDI-X Feature..................................................6
Signal Descriptions.............................................................................................................7
4.1
4.2
Signal Type Definitions .........................................................................................7
PCI Bus Interface Signals .....................................................................................8
4.2.1 Address and Data Signals .......................................................................8
4.2.2 Interface Control Signals .........................................................................8
4.2.3 System and Power Management Signals ...............................................9
Local Memory Interface Signals..........................................................................10
Test Port Signals ................................................................................................11
PHY Signals .......................................................................................................12
Power and Ground Signals .................................................................................13
4.3
4.4
4.5
4.6
5.0
Media Access Control Functional Description..................................................................15
5.1
Device Initialization..............................................................................................15
5.1.1 Initialization Effects.................................................................................15
PCI Interface .......................................................................................................16
5.2.1 Bus Operations.......................................................................................16
5.2.2 Clock Run Signal....................................................................................24
5.2.3 Power Management Event.....................................................................25
PCI Power Management .....................................................................................25
5.3.1 Power States..........................................................................................25
5.3.2 Wake-up Events.....................................................................................29
Parallel Flash.......................................................................................................30
Serial EEPROM Interface....................................................................................30
5.5.1 EEPROM Address Map..........................................................................32
10/100 Mbps CSMA/CD Unit...............................................................................32
5.6.1 Full Duplex .............................................................................................33
5.6.2 Flow Control ...........................................................................................33
5.6.3 Address Filtering Modifications ..............................................................33
5.6.4 VLAN Support ........................................................................................33
5.2
5.3
5.4
5.5
5.6
Datasheet
iii
INTEL [ INTEL ]
