Networking Silicon — 82551IT
2.0
Architectural Overview
The Intel® 82551IT is divided into four main subsystems: a parallel subsystem, a FIFO subsystem,
a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/
100 Mbps physical layer (PHY) unit.
2.1
Parallel Subsystem Overview
The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
Flash/EEPROM interface. The parallel subsystem also interfaces to the FIFO subsystem, passing
data (such as transmit, receive, and configuration data) and command and status parameters
between these two blocks.
The PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant
with the PCI Bus Specification, Revision 2.2. The 82551IT provides 32 bits of addressing and data,
as well as the PCI control interface. As a PCI target, it conforms to the PCI configuration scheme,
which allows all accesses to the 82551IT to be automatically mapped into free memory and I/O
space upon initialization of a PCI system. When transmit and receive data is processed, the
82551IT operates as a master on the PCI bus, initiating zero wait state transfers.
The 82551IT Control/Status Register Block is part of the PCI target element. The Control/Status
Register block consists of the following 82551IT internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPROM Control, and Management Data Interface (MDI) Control.
An embedded micromachine consisting of independent transmit and receive processing units allow
the 82551IT to execute commands and receive incoming frames with no real time CPU
intervention.
The 82551IT contains a multiplexed interface to connect an external serial EEPROM and Flash
memory. The Flash interface, which can also be used to connect to any standard 8-bit device,
provides up to 128 KB of addressing to the Flash. Both read and write accesses are supported. The
Flash can be used for remote boot functions, network statistical and diagnostics functions, and
management functions. The Flash is mapped into host system memory (anywhere within the 32-bit
memory address space) for software accesses. It is also mapped into an available boot expansion
ROM location during boot time of the system. More information on the Flash interface is detailed
in Section 5.4, “Parallel Flash”. The serial EEPROM is used to store relevant information for a
LAN connection such as node address, as well as board manufacturing and configuration
information. Both read and write accesses to the EEPROM are supported by the 82551IT.
Information on the EEPROM interface is detailed in Section 5.5, “Serial EEPROM Interface”.
2.2
FIFO Subsystem Overview
The 82551IT FIFO subsystem consists of independent 3 KB transmit and receive FIFOs. Each
FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames
queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe
Spacing (IFS). The FIFOs allow the 82551IT to withstand long PCI bus latencies without losing
incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:
Datasheet
3
INTEL [ INTEL ]
