80C186EC/188EC, 80L186EC/188EC
Table 5. QFP Pin Names with Package Location
AD Bus
Name
Bus Control
Name
Processor Control
Name Pin
RESIN
I/O
Name
UCS
LCS
Pin
Pin
Pin
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
76
75
74
73
69
68
67
66
63
62
61
60
59
58
ALE
55
54
81
82
83
53
52
88
50
49
51
47
48
37
11
10
13
14
9
91
92
BHE (RFSH)
S0
S1
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST/BUSY
(TEST)
P1.7/GCS7
P1.6/GCS6
P1.5/GCS5
P1.4/GCS4
P1.3/GCS3
P1.2/GCS2
P1.1/GCS1
P1.0/GCS0
93
94
S2
RD
86
95
96
WR
READY
DEN
PEREQ (V
SS
NCS (N.C.)
)
84
38
87
12
85
33
34
35
36
43
44
45
46
97
98
AD8 (A8)
AD9 (A9)
DT/R
LOCK
HOLD
HLDA
INTA
ERROR (V
PDTMR
NMI
)
99
100
CC
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13/CAS0
(A13/CAS0)
AD14/CAS1
(A14/CAS1)
AD15/CAS2
(A15/CAS2)
A16/S3
INT0
INT1
P2.7/CTS1
P2.6/BCLK1
P2.5/TXD1
P2.4/RXD1
P2.3/CTS0
P2.2/BCLK0
P2.1/TXD0
P2.0/RXD0
26
25
24
23
22
21
20
19
INT2
INT3
57
56
Power and Ground
INT4
INT5
Name
Pin
INT6
INT7
V
V
V
V
V
V
V
V
V
V
V
V
V
V
16
17
41
65
70
72
89
15
18
40
42
64
71
90
CC
CC
CC
CC
CC
CC
CC
SS
SS
SS
SS
SS
SS
SS
80
79
78
77
A17/S4
A18/S5
A19/S6/ONCE
P3.5
P3.4
32
31
30
29
28
27
P3.3/DMAI1
P3.2/DMAI0
P3.1/TXI1
P3.0/RXI1
T0IN
6
5
8
7
T0OUT
T1IN
T1OUT
DRQ0
DRQ1
DRQ2
DRQ3
1
2
3
4
WDTOUT
39
18
INTEL [ INTEL ]
