80C186EC/188EC, 80L186EC/188EC
from the top side of the component (i.e. contacts
facing down).
Pinout
Tables 3 and 4 list the pin names with package loca-
tion for the 100-pin Plastic Quad Flat Pack (PQFP)
component. Figure 4 depicts the PQFP package as
viewed from the top side of the component (i.e. con-
tacts facing down).
Tables 7 and 8 list the pin names with package loca-
tion for the 100-pin Shrink Quad Flat Pack (SQFP)
component. Figure 6 depicts the SQFP package as
viewed from the top side of the component (i.e., con-
tacts facing down).
Tables 5 and 6 list the pin names with package loca-
tion for the 100-pin EIAJ Quad Flat Pack (QFP) com-
ponent. Figure 5 depicts the QFP package as viewed
Table 3. PQFP Pin Functions with Location
Bus Control Processor Control
Name Name Pin
ALE
AD Bus
Name
I/O
Name
UCS
LCS
Pin
Pin
Pin
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
73
72
71
70
66
65
64
63
60
59
58
57
56
55
52
51
78
79
80
50
49
85
47
46
48
44
45
34
RESIN
8
7
88
89
BHE (RFSH)
S0
S1
RESOUT
CLKIN
10
11
6
OSCOUT
CLKOUT
TEST/BUSY
(TEST)
P1.7/GCS7
P1.6/GCS6
P1.5/GCS5
P1.4/GCS4
P1.3/GCS3
P1.2/GCS2
P1.1/GCS1
P1.0/GCS0
90
91
92
93
94
95
96
97
S2
RD
83
WR
READY
DEN
PEREQ (V
SS
NCS (N.C.)
)
81
35
84
9
AD8 (A8)
AD9 (A9)
DT/R
LOCK
HOLD
HLDA
INTA
ERROR (V
PDTMR
NMI
)
CC
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13/CAS0
(A13/CAS0)
AD14/CAS1
(A14/CAS1)
AD15/CAS2
(A15/CAS2)
A16/S3
82
30
31
32
33
40
41
42
43
INT0
INT1
P2.7/CTS1
P2.6/BCLK1
P2.5/TXD1
P2.4/RXD1
P2.3/CTS0
P2.2/BCLK0
P2.1/TXD0
P2.0/RXD0
23
22
21
20
19
18
17
16
INT2
INT3
54
53
Power and Ground
INT4
INT5
Name
Pin
INT6
INT7
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
13
14
38
62
67
69
86
12
15
37
39
61
68
87
77
76
75
74
A17/S4
A18/S5
A19/S6/ONCE
P3.5
P3.4
29
28
27
26
25
24
P3.3/DMAI1
P3.2/DMAI0
P3.1/TXI1
P3.0/RXI1
T0IN
3
2
5
4
T0OUT
T1IN
T1OUT
DRQ0
DRQ1
DRQ2
DRQ3
98
99
100
1
WDTOUT
36
15
INTEL [ INTEL ]
