80C186EC/188EC, 80L186EC/188EC
PCB
PCB
PCB
PCB
Function
Function
Function
Function
Offset
Offset
Offset
Offset
00H
02H
04H
06H
08H
Master PIC Port 0
Master PIC Port 1
Slave PIC Port 0
Slave PIC Port 1
Reserved
40H
42H
44H
46H
48H
4AH
T2 Count
T2 Compare
Reserved
80H
82H
84H
86H
88H
8AH
8CH
8EH
90H
92H
94H
96H
98H
9AH
9CH
9EH
A0H
A2H
A4H
A6H
GCS0 Start
GCS0 Stop
GCS1 Start
GCS1 Stop
GCS2 Start
GCS2 Stop
GCS3 Start
GCS3 Stop
GCS4 Start
GCS4 Stop
GCS5 Start
GCS5 Stop
GCS6 Start
GCS6 Stop
GCS7 Start
GCS7 Stop
LCS Start
C0H DMA 0 Source Low
C2H DMA 0 Source High
C4H
DMA 0 Dest. Low
T2 Control
C6H DMA 0 Dest. High
Port 3 Direction
Port 3 Pin State
C8H
CAH
CCH
CEH
DMA 0 Count
DMA 0 Control
DMA Module Pri.
DMA Halt
0AH SCU Int. Req. Ltch.
0CH DMA Int. Req. Ltch.
0EH TCU Int. Req. Ltch.
4CH Port 3 Mux Control
4EH
50H
52H
Port 3 Data Latch
Port 1 Direction
Port 1 Pin State
10H
12H
14H
16H
18H
1AH
1CH
1EH
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
46H
38H
3AH
3CH
3EH
Reserved
Reserved
D0H DMA 1 Source Low
D2H DMA 1 Source High
Reserved
54H Port 1 Mux Control
D4H
DMA 1 Dest. Low
Reserved
56H
58H
5AH
Port 1 Data Latch
Port 2 Direction
Port 2 Pin State
D6H DMA 1 Dest. High
Reserved
D8H
DAH
DCH
DEH
DMA 1 Count
DMA 1 Control
Reserved
Reserved
Reserved
5CH Port 2 Mux Control
Reserved
5EH
60H
62H
64H
66H
68H
6AH
6CH
6EH
70H
72H
74H
76H
78H
7AH
7CH
7EH
Port 2 Data Latch
SCU 0 Baud
SCU 0 Count
SCU 0 Control
SCU 0 Status
SCU 0 RBUF
SCU 0 TBUF
Reserved
Reserved
WDT Reload High
WDT Reload Low
WDT Count High
WDT Count Low
WDT Clear
E0H DMA 2 Source Low
E2H DMA 2 Source High
LCS Stop
UCS Start
E4H
DMA 2 Dest. Low
UCS Stop
E6H DMA 2 Dest. High
A8H Relocation Register
E8H
EAH
ECH
EEH
DMA 2 Count
DMA 2 Control
Reserved
WDT Disable
Reserved
AAH
ACH
AEH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
T0 Count
SCU 1 Baud
SCU 1 Count
SCU 1 Control
SCU 1 Status
SCU 1 RBUF
SCU 1 TBUF
Reserved
B0H Refresh Base Addr.
F0H DMA 3 Source Low
F2H DMA 3 Source High
T0 Compare A
T0 Compare B
T0 Control
B2H
B4H
B6H
B8H
BAH
BCH
BEH
Refresh Time
Refresh Control
Refresh Address
Power Control
Reserved
F4H
DMA 3 Dest. Low
F6H DMA 3 Dest. High
T1 Count
F8H
FAH
FCH
FEH
DMA 3 Count
DMA 3 Control
Reserved
T1 Compare A
T1 Compare B
T1 Control
Step ID
Reserved
Powersave
Reserved
Figure 3. Peripheral Control Block Registers
6
INTEL [ INTEL ]
