80C186EC/80C188EC and 80L186EC/80L188EC
16-BIT HIGH-INTEGRATION
EMBEDDED PROCESSOR
CONTENTS
PAGE
CONTENTS PAGE
Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
80C186EC CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4
Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
I
versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 29
CC
PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 29
AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
AC CharacteristicsÐ80C186EC25 ÀÀÀÀÀÀÀÀÀ 30
AC CharacteristicsÐ80C186EC20/13 ÀÀÀÀÀ 32
AC CharacteristicsÐ80L186EC13 ÀÀÀÀÀÀÀÀÀ 33
AC CharacteristicsÐ80L186EC16 ÀÀÀÀÀÀÀÀÀ 34
Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35
Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
80C186EC PERIPHERAL
ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Programmable Interrupt Controllers ÀÀÀÀÀÀÀÀÀ 7
Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Watchdog Timer Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
80C187 Interface (80C186EC only) ÀÀÀÀÀÀÀÀÀ 8
ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43
EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50
INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 51
ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57
REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57
PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
Package Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀ 24
ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 25
Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
2
INTEL [ INTEL ]
