80C186XL/80C188XL
Table 3. Pin Descriptions (Continued)
Output
Pin
Pin
Input
Type
Pin Description
Name
Type
States
SRDY
I
S(L)
Ð
Synchronous Ready informs the processor that the addressed
memory space or I/O device will complete a data transfer. The
SRDY pin accepts an active-HIGH input synchronized to CLKOUT.
The use of SRDY allows a relaxed system timing over ARDY. This
is accomplished by elimination of the one-half clock cycle required
to internally synchonize the ARDY input signal. Connecting SRDY
high will always assert the ready condition to the CPU. If this line is
unused, it should be tied LOW to yield control to the ARDY pin.
LOCK
O
O
Ð
Ð
H(Z)
R(Z)
LOCK output indicates that other system bus masters are not to
gain control of the system bus. LOCK is active LOW. The LOCK
signal is requested by the LOCK prefix instruction and is activated
at the beginning of the first data cycle associated with the
instruction immediately following the LOCK prefix. It remains active
until the completion of that instruction. No instruction prefetching
will occur while LOCK is asserted.
S0
S1
S2
H(Z)
R(1)
Bus cycle status S0–S2 are encoded to provide bus-transaction
information:
Bus Cycle Status Information
S2
S1
S0
Bus Cycle Initiated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
S2 may be used as a logical M/IO indicator, and S1 as a DT/R
indicator.
HOLD
HLDA
I
A(L)
Ð
Ð
HOLD indicates that another bus master is requesting the local bus.
The HOLD input is active HIGH. The processor generates HLDA
(HIGH) in response to a HOLD request. Simultaneous with the
issuance of HLDA, the processor will float the local bus and control
lines. After HOLD is detected as being LOW, the processor will
lower HLDA. When the processor needs to run another bus cycle, it
will again drive the local bus and control lines.
O
H(1)
R(0)
In Enhanced Mode, HLDA will go low when a DRAM refresh cycle
is pending in the processor and an external bus master has control
of the bus. It will be up to the external master to relinquish the bus
by lowering HOLD so that the processor may execute the refresh
cycle.
NOTE:
Pin names in parentheses apply to the 80C188XL.
13
13
INTEL [ INTEL ]
