80C186XL/80C188XL
Table 3. Pin Descriptions (Continued)
Pin
Pin
Input Output
Pin Description
Name
Type Type States
BHE
(RFSH)
O
H(Z)
R(Z)
The BHE (Bus High Enable) signal is analogous to A0 in that it is
used to enable data on to the most significant half of the data bus,
pins D15–D8. BHE will be LOW during T when the upper byte is
1
transferred and will remain LOW through T and T . BHE does not
W
3
need to be latched. On the 80C188XL, RFSH is asserted LOW to
indicate a refresh bus cycle.
In Enhanced Mode, BHE (RFSH) will also be used to signify DRAM
refresh cycles. A refresh cycle is indicated by both BHE (RFSH) and
A0 being HIGH.
80C186XL BHE and A0 Encodings
BHE
A0
Function
Value Value
0
0
0
1
Word Transfer
Byte Transfer on upper half of data bus
(D15–D8)
1
1
0
1
Byte Transfer on lower half of data bus (D –D )
7 0
Refresh
ALE/QS0
WR/QS1
O
O
H(0)
R(0)
Address Latch Enable/Queue Status 0 is provided by the processor
to latch the address. ALE is active HIGH, with addresses guaranteed
valid on the trailing edge.
H(Z)
R(Z)
Write Strobe/Queue Status 1 indicates that the data on the bus is to
be written into a memory or an I/O device. It is active LOW. When
the processor is in Queue Status Mode, the ALE/QS0 and WR/QS1
pins provide information about processor/instruction queue
interaction.
QS1
QS0
Queue Operation
0
0
1
1
0
1
1
0
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue
RD/QSMD
O
H(Z)
R(1)
Read Strobe is an active LOW signal which indicates that the
processor is performing a memory or I/O read cycle. It is guaranteed
not to go LOW before the A/D bus is floated. An internal pull-up
ensures that RD/QSMD is HIGH during RESET. Following RESET
the pin is sampled to determine whether the processor is to provide
ALE, RD, and WR, or queue status information. To enable Queue
Status Mode, RD must be connected to GND.
ARDY
I
A(L)
S(L)
Asynchronous Ready informs the processor that the addressed
memory space or I/O device will complete a data transfer. The
ARDY pin accepts a rising edge that is asynchronous to CLKOUT
and is active HIGH. The falling edge of ARDY must be synchronized
to the processor clock. Connecting ARDY HIGH will always assert
the ready condition to the CPU. If this line is unused, it should be tied
LOW to yield control to the SRDY pin.
NOTE:
Pin names in parentheses apply to the 80C188XL.
12
12
INTEL [ INTEL ]
