8XC152JA JB JC JD
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 4 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the Data
Sheet must be observed
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts-up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the V
IL
and V
IH
specifications the capacitance will not ex-
ceed 20 pF
270431 –6
Figure 4 External Clock Drive
IDLE MODE
In Idle Mode the CPU puts itself to sleep while most
of the on-chip peripherals remain active The major
peripherals that do not remain active during Idle are
the DMA channels The Idle Mode is invoked by
software The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset
POWER DOWN MODE
In Power Down Mode the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained The mode Power
Down is invoked by software The Power Down
Mode can be terminated only by a hardware reset
270431 –5
Figure 3 Using the On-Chip Oscillator
Table 3 Status of the External Pins During Idle and Power Down Modes
80C152JA 83C152JA 80C152JC 83C152JC
Mode
Idle
Idle
Power Down
Power Down
Program
Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
Port 0
Data
Float
Data
Float
Port 1
Data
Data
Data
Data
Port 2
Data
Address
Data
Data
Port 3
Data
Data
Data
Data
Port 4
Data
Data
Data
Data
80C152JB 80C152JD
Mode
Idle
Idle
Power Down
Power Down
Instruction
ALE PSEN EPSEN Port 0 Port 1
Bus
P0 P2
P5 P6
P0 P2
P5 P6
1
1
0
0
1
1
0
1
1
1
1
0
Float
Data
Float
Data
Data
Data
Data
Data
Port 2
Address
Data
Data
Data
Port 3 Port 4 Port 5
Data
Data
Data
Data
Data
Data
Data
Data
0FFH
0FFH
0FFH
Port 6
0FFH
0FFH
0FFH
0FFH Address
NOTE
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook and Application
Note AP-252 ‘‘Designing with the 80C51BH ’’
Note difference of logic level of PSEN during Power Down for ROM JA JC and ROM emulation mode for JC JD
7
INTEL [ INTEL CORPORATION ]
