80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 2.
80960Jx Block Diagram
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Control
21
Address/
Data Bus
32
CLKIN
PLL, Clocks,
Power Mgmt
32-bit buses
address / data
Instruction Cache
80960JA - 2K
80960JF/JD - 4K
TAP
5
Boundary Scan
Controller
80960JT - 16K
Two-Way Set Associative
Instruction Sequencer
Constants
Control
Two 32-Bit
Timers
Interrupt
Port
9
8-Set
Local Register Cache
Multiply
Divide
Unit
Execution
and
Address
Generation
Unit
effective
address
SRC1
SRC2
SRC1
SRC2
DEST
DEST
Programmable
Interrupt Controller
Memory
Interface
Unit
Memory-Mapped
Register Interface
128
Global / Local
Register File
SRC1
SRC2 DEST
32-bit Address
32-bit Data
SRC1
DEST
1K Data RAM
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JT - 4K
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
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Core operates at the bus speed with the 80960JA/JF
Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
Two-way set associative, integrated instruction cache
Direct-mapped, integrated data cache
1 Kbyte integrated data RAM delivers zero wait state program data
Advance Information Datasheet
9
INTEL [ INTEL CORPORATION ]
