80960JA/JF/JD/JT 3.3 V Microprocessor
The 80960Jx rapidly allocates and deallocates local register sets during context switches. The
processor needs to flush a register set to the stack only when it saves more than seven sets to its
local register cache.
A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full
complement of control signals simplifies the connection of the 80960Jx to external components.
The user programs physical and logical memory attributes through memory-mapped control
registers (MMRs) — an extension not found on the i960 Kx, Sx or Cx processors. Physical and
logical configuration registers enable the processor to operate with all combinations of bus width
and data object alignment. The processor supports a homogeneous byte ordering model.
This processor integrates two important peripherals: a timer unit, and an interrupt controller. These
and other hardware resources are programmed through memory-mapped control registers, an
extension to the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and
general-purpose system timing. These operate in either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.
The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The
ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt
latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock
tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be
dedicated to high-priority interrupts to further reduce latency. Acting independently from the core,
the ICU compares the priorities of posted interrupts with the current process priority, off-loading
this task from the core. The ICU also supports the integrated timer interrupts.
The 80960Jx features a Halt mode designed to support applications where low power consumption
is critical. The
halt
instruction shuts down instruction execution, resulting in a power savings of up
to 90 percent.
The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.
The
Solutions960
®
program features a wide variety of development tools which support the i960
processor family. Many of these tools are developed by partner companies; some are developed by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.
8
Advance Information Datasheet
INTEL [ INTEL CORPORATION ]
